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authorH.J. Lu <hjl.tools@gmail.com>2020-12-23 06:49:04 -0800
committerLasse Collin <lasse.collin@tukaani.org>2020-12-23 17:13:33 +0200
commit4fd79b90c52396d70e0b1206ceb1a873a0ad2589 (patch)
treea6e484849843757e8df88f9011c0a027beee17aa /src
parentUpdate THANKS. (diff)
downloadxz-4fd79b90c52396d70e0b1206ceb1a873a0ad2589.tar.xz
liblzma: Enable Intel CET in x86 CRC assembly codes
When Intel CET is enabled, we need to include <cet.h> in assembly codes to mark Intel CET support and add _CET_ENDBR to indirect jump targets. Tested on Intel Tiger Lake under CET enabled Linux.
Diffstat (limited to 'src')
-rw-r--r--src/liblzma/check/crc32_x86.S9
-rw-r--r--src/liblzma/check/crc64_x86.S9
2 files changed, 18 insertions, 0 deletions
diff --git a/src/liblzma/check/crc32_x86.S b/src/liblzma/check/crc32_x86.S
index 632c7b37..7814beca 100644
--- a/src/liblzma/check/crc32_x86.S
+++ b/src/liblzma/check/crc32_x86.S
@@ -51,6 +51,14 @@ init_table(void)
* extern uint32_t lzma_crc32(const uint8_t *buf, size_t size, uint32_t crc);
*/
+/* When Intel CET is enabled, include <cet.h> in assembly code to mark
+ Intel CET support. */
+#ifdef __CET__
+# include <cet.h>
+#else
+# define _CET_ENDBR
+#endif
+
/*
* On some systems, the functions need to be prefixed. The prefix is
* usually an underscore.
@@ -83,6 +91,7 @@ init_table(void)
ALIGN(4, 16)
LZMA_CRC32:
+ _CET_ENDBR
/*
* Register usage:
* %eax crc
diff --git a/src/liblzma/check/crc64_x86.S b/src/liblzma/check/crc64_x86.S
index f5bb84b9..7ee08f64 100644
--- a/src/liblzma/check/crc64_x86.S
+++ b/src/liblzma/check/crc64_x86.S
@@ -41,6 +41,14 @@ init_table(void)
* extern uint64_t lzma_crc64(const uint8_t *buf, size_t size, uint64_t crc);
*/
+/* When Intel CET is enabled, include <cet.h> in assembly code to mark
+ Intel CET support. */
+#ifdef __CET__
+# include <cet.h>
+#else
+# define _CET_ENDBR
+#endif
+
/*
* On some systems, the functions need to be prefixed. The prefix is
* usually an underscore.
@@ -73,6 +81,7 @@ init_table(void)
ALIGN(4, 16)
LZMA_CRC64:
+ _CET_ENDBR
/*
* Register usage:
* %eax crc LSB